The present invention relates to a method of manufacturing an integrated circuit device, and more particularly to a method of forming contact pads without photo-mask and etching processes.
To achieve greater integration in integrated circuits, design rules for semiconductor devices have reduced the dimensions of the elements of the devices to a degree that alignment of structures such as a contact plug with an underlying interconnect layer is critical. Accordingly, sub-quarter micron semiconductor devices such as Gbit DRAMs need manufacturing technology that self-aligns structures.
FIGS. 1A to 1F illustrate a conventional method for forming contact pads in a semiconductor device. Referring to FIG. 1A, a pad oxide layer 12 and a pad nitride layer 14 are sequentially formed on a semiconductor substrate 10. Pad nitride layer 14 and pad oxide layer 12 are etched using a mask (not shown) to expose a portion of substrate 10, and the exposed portion of substrate 10 is further etched using pad nitride layer 14 and pad oxide layer 12 as an etching mask for formation of a trench 16.
Referring to FIG. 1B, a thermal oxide layer 17 is grown in trench 16. A trench liner nitride layer 18 is formed on thermal oxide layer 17, and deposition of an insulating layer 20 fills trench 16. Then, a planarization process such as CMP (chemical mechanical polishing) removes upper portions of insulating layer 20 until pad nitride layer 14 is exposed, leaving trench isolation 21. After the completion of trench isolation 21, pad nitride layer 14 and pad oxide layer 12 are removed.
Referring to FIG. 1C, a gate oxide layer 22, a polycide layer 24, and a nitride layer 26 are sequentially deposited on the structure of FIG. 1B. Then, photo-masking and etching selectively etch nitride layer 26, polycide 24 and gate oxide layer 22 to form patterned gate electrode layers 27. Gate sidewall spacers 28 can be formed on the sidewalls of gate electrode layers 27, and impurity ions are implanted into substrate 10 to form source/drain regions 30 adjacent to gate electrode layers 27 in substrate 10.
Referring to FIGS. 1D to 1F, after the formation of source/drain regions 30, an oxide layer 32 is deposited on the structure of FIG. 1C and planarized as shown in FIG. 1D. Oxide layer 32 is selectively etched using conventional photo-masking and etching to form contact openings 34 which expose source/drain regions 30 of substrate 10. A conductive material layer 40 is then deposited on oxide layer 32 so as to fill contact openings 34. Patterning layer 40 forms contact pads 36a and 36b. In an exemplary semiconductor device such as a DRAM, contact pad 36a electrically connects to an overlying structure such as a bit line (not shown), and contact pad 36b, which is between gate electrode layer 27 and trench isolation 21, electrically connects to and overlying structures such as a storage node (not shown).
In the manufacturing processes described, if the mask for the etching of oxide layer 32 is misaligned relative to patterned gate electrode layer 27, etching can remove portions of silicon nitride layer 26 and thereby expose portions of polycide layer 24. This leads to a short between gate electrode (polycide layer 24) and contact pads 36a and 36b that are formed of conductive material layer 40.
A method in accordance with an embodiment of the invention forms self-aligned contact pads in an integrated circuit device such as a DRAM and avoids shorts between contact pads and conductive structures such as gate electrodes. The self-aligned process avoids electrical shorts that can result from misalignment in conventional contact formation processes.
A method in accordance with an embodiment of the present invention forms contact pads without forming a planar insulating layer and without subsequent photo-masking and etching of the planar insulating layer. The method forms spaced apart gate electrode structures on an integrated circuit device. The gate electrodes can be insulated using sidewall spacers on sidewalls of the gate electrode structures. A process such as vapour deposition fills spaces between gate electrode structures and between a gate electrode structure and a device isolation region with conductive material for contact pads. Etching the deposited conductive material forms contact pads in the spaces between the gate electrode structures.
Gate electrode structures can be made of stacked layers including, for example, a polysilicon layer, a metal silicide layer, and a nitride capping layer. The polysilicon may be from the mask used for forming the device isolation, i.e., trench isolation.
In one specific embodiment, an oxide layer and a first doped polysilicon layer are formed on a substrate. Photo-masking and etching processes remove portions of the first doped polysilicon, the oxide layer and the substrate to form a trench. An insulating trench fill layer such as an O3-TEOS layer is deposited in the trench and on the doped polysilicon layer. The trench fill layer is then planarized down to the first polysilicon layer, thereby forming trench isolation which electrically isolates active regions of the substrate. Filling the trench with the insulating trench fill layer may be preceded by formation of thermal oxide in the trench and forming a silicon nitride layer thereon. The thermal oxide layer relieves substrate damage from previous etching of the substrate. The silicon nitride in the trench relieves stress applied to the trench walls.
A conductive layer such as metal silicide or second doped polysilicon is deposited on the first doped polysilicon and the trench isolation. A silicon nitride layer is then deposited on the conductive layer. Using photolithography, selected portions of the layers already formed on the substrate are etched to form spaced apart gate electrode structures and trench isolation that extends above the surface of the substrate.
In one embodiment, each gate electrode structure includes an oxide layer, a first doped polysilicon, a metal silicide layer, and a nitride layer. The oxide layer insulates gate electrode structures from the substrate. Sidewall insulation is formed on the gate electrode structures which still leaves portions of the substrate exposed between the gate electrodes.
Spaces between adjacent gate electrode structures and between gate electrode structure and trench isolation are filled with conductive material such as a third doped polysilicon layer. The third doped polysilicon is then etched to form contact pads in spaces between adjacent gate electrode structures and in spaces between the trench isolation and gate electrode structures. Patterning the third polysilicon layer also electrically isolates the contact pads from each other.